Design for Test
DFT Training Course
AGS QA Semiconductor approved training
Best DFT Training Institute in Dhaka DFT Training Course
COURSE DESCRIPTION
Design For Testability (DFT) is a specialization in the SOC design cycle, to detect the manufacturing defects in a design. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time. DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, memories and interconnects. Online DFT training course is designed as per the current industry requirements with multiple hands on projects based on SCAN, ATPG, JTAG and MBIST
Best DFT training institute with placement
Eligibility:
Fresh Graduate in:
- Electronic & Electricals (E&E)
- Electronic Science and Technology
- Communication Engineering
- Microelectronics Science and Engineering
- Electronic or Computer or Information Science and Technology
- Other electronics-related disciplines
- Unemployed Engineering Graduate Individual below age of 30
Course Highlights:
- Review, analyse and propose changes to improve testability and implement them by doing Scan, ATPG and Simulations.
- Analyse the DRC issues and can be able to find the solution during scan and ATPG.
- Analyse test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
- Generate the patterns for both stuck-at and at speed testing of the design for optimal test cost.
- Understanding and applying debugging techniques used in debugging test on silicon in simulation environment.
- 24×7 Lab Support with Lab practice handouts and course material delivery.
- Industry standard project execution with Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
- Soft skills development, complete suite of job oriented physical design training with 100% placement assistance.
Best DFT training institute with placement
COURSE CURRICULUM
Module 1: Basics of Unix/Linux
- 1 - Introduction and Working knowledge of UNIX/LINUX commands
- 2 - File handling skills in UNIX/LINUX 3 Introduction to programming languages used in IC-Design
Module 2: Basics of CMOS
- 3 - MOSFET Operation, stick diagram, IC fabrication process
- 4 - Formation of Digital (NAND AND OR NOR etc) logic using CMOS
Module 3: Design and Tech libraries
- 5 - Characterization of Digital standard cells and Library file information
- 6 - Technology File information, LEF file information, QRC Tech file process
- 7 - Basics RTL coding and RTL language like Verilog, VHDL, System Verilog
Module 4: Synthesis Part-1
- 8 - Inputs and Outputs understanding
- 9 - Constraints development and understanding
- 10 - Optimization techniques (uniqify, preserve, flatten )
- 11 - DFT basics
Module 5: Synthesis Part-2
- 12 - Low power implementation techniques
- 13 - Sanity checks like check Design, lint report
- 14 - Derive environment features
- 15 - Generic, map, incremental
- 16 - Wireload model, PLE, Physical, Spatial
Module 6: Logical Equivalence
- 17 - Inputs and outputs understanding
- 18 - Intent and comparison understanding
Module 7: Static Timing Analysis Part-1
- 19 - Basic understanding of transition/slew, capacitance, leakage power, internal power, On-Chip-Variation (derate, AOCV, LVF)
- 20 - Library file difference NLDM, CCS, ECSM, LVF
- 21 - Timing concepts understanding like setup, hold, recovery, removal, pulse_width, clock gating check
Module 8: Static Timing Analysis Part-2
- 22 - PLL jitter understanding and uncertainty calculations
- 23 - IO budgeting
- 24 - Different Timing Modes understanding
- 25 - ECO generation
Module 9: Physical Design
- 26 - Floor planning concepts and IO placement
- 27 - Power planning
- 28 - Placement strategies like region, fence, blockages, padding, bump, don’t touch, filler gap
- 29 - DRV optimization, Buffer tree synthesis
- 30 - Clock tree synthesis and clock latency calculations
- 31 - Routing design and optimization
- 32 - Antenna
- 33 - ECO Timing closure and implementation cycle
Module 10: Physical Design Verification
- 34 - Design Rule Checks understanding and importance
- 35 - Layout Versus Schematic and difference with respect to LEC
- 36 - Electrical Rule Checks
- 37 - IR Drop analysis - Static and Dynamic
Module 11: Industry standard Project Execution
- 38 - Industry Standard Physical Design Live Project
Module 12: Mock Interviews & Personality improvement
Physical Design Training course mainly focused on giving complete hands on experience to physical design and physical verification training flow with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from partitioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.
It is extensive training for students in the field of electrical and electronics. AGS QA VLSI ranks among the top 10 physical design training institutes in the Dhaka.
30 Students
Duration: 5 Months
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