RTL Coding and FPGA Design
RTL Coding and FPGA Design
AGS QA Semiconductor approved training
RTL Coding and FPGA Design Training Courses in Bangladesh
COURSE DESCRIPTION
RTL Coding and FPGA Design course has been designed to help to the beginners in the area of RTL coding and FPGA design. The course gives you the foundation for FPGA design in Embedded Systems along with practical design skills. By end of the course you will learn what FPGA, how to select the best FPGA architecture for a given application, solve critical digital design problems using FPGAs. As a part of the course, you will also learn to use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or as an engineer looking at a career change, this is a great course to enhance your career opportunities.
FPGA Design, RTL Coding & RTL Design Training Institute
Eligibility:
Fresh Graduate in:
- Electronic & Electricals (E&E)
- Electronic Science and Technology
- Communication Engineering
- Microelectronics Science and Engineering
- Electronic or Computer or Information Science and Technology
- Other electronics-related disciplines
- Unemployed Engineering Graduate Individual below age of 30
Course Highlights:
- Deep understanding of digital logic design
- Knowledge of FPGA/ASIC design flow
- In depth knowledge of Verilog HDL – RTL coding & synthesis
- Fare understanding of creating power friendly RTL design
- Good understanding of FPGA implementation and debugging on Xilinx evaluation board.
- Acquire skills to do minor/major
- 24×7 Lab Support with Lab practice handouts and course material delivery.
- Industry standard project execution, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
- Soft skills development, complete suite of job oriented ASIC Verification training with 100% placement assistance.
COURSE CURRICULUM
Module 1: Basics of Unix/Linux
- 1 - Introduction to Unix/Linux OS Architecture
- 2 - UNIX Directory Structures and Unix Commands
- 3 - UNIX Shells
- 4 - LAB Exercises
Module 2 : Digital logic Fundamentals and Advanced Digital Design
- 5 - Digital Number System, Binary logic gates & Boolean algebra
- 6 - Digital Number System, Binary logic gates & Boolean algebra
- 7 - Combinational and Sequential circuit designs
- 8 - Finite state machine optimization
• Module 3 : ASIC/FPGA/SOC Design Flow
- 9 - What is FPGA? What is ASIC?
- 10 - Overview of FPGA/ASIC/SOC design flow
- 11 - FPGA Vs ASIC comparison summary
- 12 - How to choose between FPGA or ASIC
Module 4 : RTL Coding - Verilog HDL
- 13 - Introduction to RTL coding
- 14 - Overview of digital design with verilog HDL
- 15 - Design modelling with examples
- 16 - Tasks and functions
- 17 - RTL Simulation and synthesis
- 18 - Creating power friendly RTL & Timing analysis
- 19 - Module level test bench development
- 20 - RTL design optimization techniques
Module 5 : Programmable Logic Design
- 21 - Read only Memories (ROM)
- 22 - PALs & PALs
- 23 - CPLDs & FPGAs
Module 6 : FPGA Design Example
- 24 - FPGA Architecture
- 25 - Dual port memory - Example design
- 26 - FPGA design Flow
- 27 - Bit file generation & downloading the Hex file to FPGA device
- 28 - FPGA validation through chipscope & DS5 debugger
- 29 - Project work and board bring up
Module 7 : Advanced FPGA Concepts
- 30 - Overview of 7 series FPGA architecture
- 31 - Introduction to Zynq FPGA-SoC --> SoCs with Hardware and Software programmability
- 32 - Efficient FPGA RTL coding for design synthesis & Implementation
Module 8 : Xilinx Design Implementation tools & Xilinx's Evalution board for Prototyping
- 33 - Xilinx tool introduction & Installation
- 34 - RTL simulation - Qsim from Mentor graphics
- 35 - Hands-on experience in using vivado design suite for design synthesis and Implementation
- 36 - Hands-on experience in using chipscope and DS5 debugger for debugging functioality failures
Module 9 : Mini & Major Projects on FPGA Device
- 37 - IR Drop analysis - Static and Dynamic
- 38 - Industry Standard Physical Design Live Project
Module 12: Mock Interviews & Personality improvement
Physical Design Training course mainly focused on giving complete hands on experience to physical design and physical verification training flow with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from partitioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.
It is extensive training for students in the field of electrical and electronics. AGS QA VLSI ranks among the top 10 physical design training institutes in the Dhaka.
30 Students
Duration: 5 Months
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