Universal Verification Methodology
Universal Verification Methodology
AGS QA Semiconductor approved training
Universal Verification Methodology (UVM) Training in Bangladesh
COURSE DESCRIPTION
The Accelerate Universal Verification Methodology (UVM) standard defines a methodology for using SystemVerilog for the verification of complex designs. Get UVM training from one of the most reliable UVM Training Institutes. UVM enables engineers to write thorough and reusable test environment is a robust methodology with many advanced features. In this System Verilog UVM training, engineers will learn to apply the UVM for transaction level verification, constrained random test generation, coverage, and score boarding. Topics include UVM test phases, UVM class libraries, UVM utilities, UVM factories, UVM sequencers, UVM drivers, UVM Monitors, UVM scoreboards, UVM registers, and configuring UVM tests.
Advanced Universal Verification Methodology (UVM) Training
Eligibility:
Fresh Graduate in:
- Electronic & Electricals (E&E)
- Electronic Science and Technology
- Communication Engineering
- Microelectronics Science and Engineering
- Electronic or Computer or Information Science and Technology
- Other electronics-related disciplines
- Unemployed Engineering Graduate Individual below age of 30
Course Highlights:
- Classes conducted by working professionals from industry.
- All Modules include the required hands on work.
- Emphasized on UVM concepts and libraries, UVM Test bench structuring and functional coverage.
- Assignments with fully automated Verification flow. Project on Industry accepted protocols.
- Lab Support with classroom practice handouts and course material.
- Soft skills development, job oriented UVM training with 100% placement assistance.
Universal Verification Methodology (UVM) training institute with placement
COURSE CURRICULUM
Module 1: UVM Overview
- 1 - The purpose of UVM
- 2 - UVM testbench architecture
- 3 - UVM test phases
- 4 - UVM objects and components
Module 2: Rapid Review of SystemVerilog Object-Oriented Verification
- 5 - SystemVerilog’s class data type and new() constructors
- 6 - Inheritance, data hiding
- 7 - Virtual methods and polymorphism
- 8 - Specialized (parameterized) classes
- 9 - Object handle assignments and down casting
- 10 - Constrained random value generation
- 11 - Functional coverage
Module 3: UVM First Look
- 12 - UVM class library
- 13 - uvm_object class
- 14 - uvm_component class
- 15 - Registering UVM components with the factory
- 16 - Virtual interfaces and connecting to the DUT
- 17 - UVM print and debug utilities
- 18 - Lab: The big picture — examine all the parts of a complete UVM testbench
Module 4: UVM Sequence items and Sequences
- 19 - UVM sequence_items (transactions)
- 20 - Defining sequence_item methods
- 21 - Using sequence_item field macros
- 22 - UVM sequences of transactions
- 23 - Sequence/Driver synchronization
- 24 - Lab: Define and simulate sequence_items and sequences
Module 5: UVM Sequencers and Drivers
- 25 - UVM sequencers
- 26 - UVM drivers
- 27 - Transaction Level Modeling (TLM)
- 28 - TLM ports, exports, and analysis ports
- 29 - Lab: Define and simulate a UVM driver and sequencer
Module 6: UVM Monitors and Agents
- 30 - CUVM monitors
- 31 - Adding one or more monitor analysis ports
- 32 - Agent active and passive modes
- 33 - Lab: Defining and simulating a UVM monitor and agent
Module 7: UVM Functional Coverage
- 34 - Design Rule Checks understanding and importance
- 35 - Coverage collectors
- 36 - Where to add coverage collectors
- 37 - Enabling and disabling coverage collectors
- 38 - Lab: Define, simulate, and examine coverage
Module 8: UVM Environments, Predictors and Scoreboards
- 39 - Scoreboard fundamentals
- 40 - Predicting expected results
- 41 - Comparing expected and actual results
- 42 - Encapsulation in a test environment
- 43 - Lab: Define and simulate a UVM scoreboard and environment, and verifying the outputs of a (faulty) DUT
Module 9: UVM Tests and Advanced Sequences
- 44 - Putting everything together in a UVM test
- 45 - Running multiple tests
- 46 - Virtual sequences and sequencers
- 47 - Sequential and parallel sequences
- 48 - Sequencer arbitration modes
- 49 - Layered sequences
- 50 - Driver to sequence feedback
- 51 - Top-level modules
- 52 - Lab: Define and simulate a test that runs multiple sequences
Module 10: UVM Factory
- 53 - Understanding the UVM factory
- 54 - Registering and constructing verification components
- 55 - Factory overrides
- 56 - Using the UVM Configuration database
- 57 - Reuse and scalability considerations
- 58 - UVM messages and reports
- 59 - Lab: Define and simulate a configurable UVM test environment
- 59 - Lab: Define and simulate a configurable UVM test environment and UVM Configuration
Module 11: UVM Register Layer Overview
- 60 - When and where to use verification registers
- 61 - Register packages
- 62 - Registers and register files
- 63 - Bus translators
- 64 - Back door access
- 65 - Front door access
- 66 - Register stimulus generation
30 Students
Duration: 5 Months
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