AGS QA SEMICONDUCTOR

VLSI Chip Design Training & Physical Design Courses in Bangladesh

COURSE DESCRIPTION

Our Physical Design Training program equips semiconductor engineers with the essential knowledge and hands-on skills needed to master the complete physical design flow of ASIC and SoC projects. The course covers advanced methodologies and industry-standard EDA tools to ensure participants can deliver high-quality layouts optimized for performance, power, and area.

 

It is extensive training for students in the field of electrical and electronics. AGS QA Semiconductor ranks among the top 10 physical design training institutes in the Dhaka.

 

Industry Standard VLSI and DFT Training

Eligibility

  • B.Sc in ECE/EEE/CSE/Physics
  • M.Sc/M.S in VLSI/Embedded Systems/Digital Electronics/Physics

Course Highlights:

  • Hands-on exposure to physical design flow with industry standard EDA tools.
  • Deep understanding of various methodologies and technologies used.
  • 24×7 Lab Support with Lab practice handouts and course material delivery.
  • Industry standard project execution from RTL to gdsii training, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
  • Soft skills development, complete suite of job oriented physical design training with 100% placement assistance

 

 

COURSE CURRICULUM

Module 1: Basics of Unix/Linux

1 Introduction and Working knowledge of UNIX/LINUX commands

2 File handling skills in UNIX/LINUX 3 Introduction to programming languages used in IC-Design

Module 2: Basics of CMOS

4 MOSFET Operation, stick diagram, IC fabrication process

5 Formation of Digital (NAND AND OR NOR etc) logic using CMOS

Module 3: Design and Tech libraries

6 Characterization of Digital standard cells and Library file information

7 Technology File information, LEF file information, QRC Techfile process

8 Basics RTL coding and RTL language like Verilog, VHDL, SystemVerilog

Module 4: Synthesis Part-1

9 Inputs and Outputs understanding

10 Constraints development and understanding

11 Optimization techniques (uniqify, preserve, flatten )

12 DFT basics

Module 5: Synthesis Part-2

13 Low power implementation techniques

14 Sanity checks like checkDesign, lint report

15 Derive environment features

16 Generic, map, incremental

17 Wireload model, PLE, Physical, Spatial

Module 6: Logical Equivalence

18 Inputs and outputs understanding

19 Intent and comparison understanding

Module 7: Static Timing Analysis Part-1

20 Basic understanding of transition/slew, capacitance, leakage power, internal power, On-Chip-Variation (derate, AOCV, LVF)

21 Library file difference NLDM, CCS, ECSM, LVF

22 Timing concepts understanding like setup, hold, recovery, removal, pulse_width, clock gating check

Module 8: Static Timing Analysis Part-2

23 PLL jitter understanding and uncertainty calculations

24 IO budgeting

25 Different Timing Modes understanding

26 ECO generation

Module 9: Physical Design

27 Floor planning concepts and IO placement

28 Power planning

29 Placement strategies like region, fence, blockages, padding, bump, don’t touch, filler gap

30 DRV optimization, Buffer tree synthesis

31 Clock tree synthesis and clock latency calculations

32 Routing design and optimization

33 Antenna

34 ECO Timing closure and implementation cycle

Module 10: Physical Design Verification

35 Design Rule Checks understanding and importance

36 Layout Versus Schematic and difference with respect to LEC

37 Electrical Rule Checks

38 IR Drop analysis – Static and Dynamic

Module 11: Industry standard Project Execution

39 Industry Standard Physical Design Live Project

Module 12: Mock Interviews & Personality improvement

 

 

Physical Design Training course mainly focused on giving complete hands on experience to physical design and physical verification training flow with latest tools and full lab practice. By end of the course your will learn to work in Linux environment, understand complete physical design flow from partitioning, floor planning, power planning, timing analysis, clock tree synthesis, routing of a functional unit blocks to physical verification and sign-off checks.

 

It is extensive training for students in the field of electrical and electronics. AGS QA VLSI ranks among the top 10 physical design training institutes in the Dhaka.

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